1. Field of the Invention
The present invention relates generally to Liquid-Crystal Display (LCD) devices. More particularly, the invention relates to a substrate on which Thin-Film Transistors (TETs) are arranged in a matrix array, i.e., a TFT array substrate, and an active-matrix addressing LCD device equipped with the substrate. This substrate and device are preferably applicable to the light bulb of the projection type display device.
2. Description of the Related Art
In recent years, various types of display devices applicable to wall-hung type televisions (TVs), projection type TVs, or Office Automation (OA) equipment have been developed. To realize high-grade display devices for OA equipment or high-definition TVs (HDTVs), active-matrix addressing LCD devices utilizing TFTs as their switching elements are more promising within the conventional display devices. This is because active-matrix LCD devices have an advantage that contrast and response speed do not degrade even if the count of the scan lines is increased. Moreover, active-matrix LCD devices have another advantage that a large-sized display screen can be easily realized if they are used as the light bulb of projection-type display devices.
With the LCD device designed for the light bulb, normally, high-luminance light is inputted into the LCD device from a light source and then, the light thus inputted is controlled according to the image information while the light passes through the same device. In other words, the intensity of the light transmitted through the device is adjusted by changing the transmittance of the individual pixels by application of electric field to the respective pixels while driving the TFTs. The light passed through the device is then enlarged and projected onto a large screen by way of a projection light system including specific lenses.
The light source is located on the opposite substrate side of the LCD device while the projection light system is on the TFT-array substrate side. Thus, not only the light emitted from the light source but also the light reflected by the projection light system will enter the device.
With the active-matrix addressing LCD device, a layer of semiconductor such as amorphous silicon or polysilicon (i.e., a semiconductor layer) is used for the active layer of each TFT. If light is irradiated to the active layer, current leakage will be induced due to optical excitation. On the other hand, as described previously, high-luminance light is inputted into the LCD device for the light bulb and thus, the current leakage will be large. Since, in addition to the light from the source, the reflected light by the projection light system is irradiated to the active layer, the current leakage is likely to be larger.
Recently, there is a tendency that the projection type LCD device is designed to be more compact and to have higher luminance. Thus, the luminance of the light inputted into the device tends to be higher. From this point of view, the above-described problem about the current leakage will be more serious. To solve this problem, with prior-art active-matrix addressing LCD devices for the light bulb, light-shielding layers are provided to prevent the light from irradiating to the active layers of the TFTs.
FIG. 1 and FIGS. 2A and 2B show the schematic configuration of the TFT array substrate 100 of a prior-art LCD device of this type, in which only one pixel is illustrated for simplification. FIG. 1 is a partial plan view of the substrate 100, FIG. 2A is a cross-sectional view along the line IIA—IIA in FIG. 1, and FIG. 2B is a cross-sectional view along the line IIB—IIB in FIG. 1. These figures show the structure of one pixel, because all the pixels have the same structure.
The prior-art TFT array substrate 100 comprises a transparent plate 101, on which TFTs 131 are arranged in a matrix array. A lower light-shielding layer 103, which is made of tungsten silicide (WSi2), is formed over the plate 101 by way of a silicon dioxide (SiO2) layer 102. The plan shape of the lower light-shielding layer 103 is like a lattice, which is formed by lateral strips extending along the rows (the X direction in FIG. 1) of the matrix of the TFTs 131 and vertical strips extending along the columns (the Y direction in FIG. 1) thereof and intersecting with the lateral ones. The whole layer 103 is covered with an overlying SiO2 layer 104.
Patterned polysilicon layers 107, which serve as the active layers of the TFTs 131, are formed on the SiO2 layer 104. Each of the layers 107 has a plan shape like L.
Each of the polysilicon active layers 107 comprises an undoped channel region 107c, two lightly-doped LDD (Lightly-Doped Drain) regions 107b and 107d, a heavily-doped source region 107a, and a heavily-doped drain region 107e. The source and drain regions 107a and 107e are located at each side of the channel region 107c. The LDD region 107b is located between the source region 107a and the channel region 107c. The LDD region 107d is located between the channel region 107c and the drain region 107e. 
The source region 107a, the LDD region 107b, the channel region 107c, the LDD region 107d, and the drain region 107e are arranged along the Y direction in such a way as to overlap with the lower light-shielding layer 103. Part of the drain region 107e is extended in the X direction.
A gate dielectric layer 108 is formed on the SiO2 layer 104 to cover the underlying active layers 107.
Gate lines 109, which are made of impurity-doped polysilicon or silicide, are formed on the gate dielectric layer 108. These lines 109 are parallel to each other and extend in the X direction. Each of the lines 109 is located to overlap with the channel regions 107c of the TFTs 131 that belong to the same row of the matrix. The parts of the line 109 placed right over the regions 107c serve as gate electrodes of the corresponding TFTs 131. The lines 109 are entirely covered with a first interlayer dielectric layer 110.
Data lines 111, which are made of aluminum (Al), are formed on the first interlayer dielectric layer 110. These lines 111 are parallel to each other and extend in the Y direction. Each of the lines 111 is located to overlap with the active layers 107 of the TFTs 131 that belong to the same column of the matrix. The line 111 covers entirely the source regions 107a, the channel regions 107c, and the LDD regions 107b and 107d of the corresponding TFTs 131. The line 111 covers parts of the drain regions 107e of the corresponding TFTs 131, The line 111 is mechanically contacted with and electrically connected to the source regions 107a of the TFTs 131 that belong to the same row of the matrix by way of contact holes 121 that penetrate the first interlayer dielectric layer 110 and the gate dielectric layer 105. The lines 111 are entirely covered with a second interlayer dielectric layer 112.
A patterned black matrix layer 113, which is made of chromium (Cr), is formed on the second interlayer dielectric layer 112. The plan shape of the layer 113 is like a lattice, which is formed by lateral strips extending along the rows (the X direction in FIG. 1) of the matrix and vertical strips extending along the columns (the Y direction in FIG. 1) thereof and intersecting with the lateral ones. The layer 113 is patterned to overlap with the gate lines 109 and the data lines 111 and to cover the TFTs 131. The layer 113 serves as an upper light-shielding layer. The layer 113 is entirely covered with a third interlayer dielectric layer 114.
Pixel electrodes 115, which have an approximately rectangular plan shape, are formed on the third interlayer dielectric layer 114 The electrodes 115 are located in corresponding pixel areas 120 defined by the gate lines 109 and the data lines 111. The electrodes 115 are mechanically contacted with and electrically connected to the drain regions 107e of the corresponding TFTs 131 by way of contact holes 122 that penetrate the third interlayer dielectric layer 114, the second interlayer dielectric layer 112, the first interlayer dielectric layer 110, and the gate dielectric layer 108.
With a prior-art LCD device including the prior-art TFT array substrate 100 having the above-described structure, an opposite substrate (not shown) is coupled with the substrate 100 to form a liquid-crystal layer between these two substrates. The light entering the LCD device from the side of the opposite substrate is blocked by the black matrix layer (i.e., the upper light-shielding layer) 113. The light entering from the side of the TFT array substrate 100 is blocked by the lower light-shielding layer 103. However, there is a problem that the light entering from the side of the substrate 100 is unable to prevent sufficiently from being irradiated to the LDD regions 107b and 107b and/or the channel region 107c of the TFT 131. This is explained in more detail below with reference to FIG. 3.
As shown in FIG. 3, the light L101 entering the LCD device from the side of the opposite substrate is blocked by the black matrix layer (i.e., the upper light-shielding layer) 113. Alternately, the light L101 penetrates the substrate 100 without reflection by the lower light-shielding layer 103. This is because the widths of the layers 113 and 103 and the interval between the layers 113 and 103 are well adjusted for this purpose. The light L102 entering the LCD device from the side of the substrate 100 is blocked by the lower light-shielding layer 103.
However, as seen from FIG. 3, the light L103 entering the LCD device from the side of the TFT array substrate 100 toward the black matrix layer 113 is reflected by the layer 113 to go to the lower light shielding layer 103. Then, the light L103 travels the space between the layer 103 and the data line 111 through multiple reflections and finally, it reaches the LDD region 107b. Moreover, the light L104 entering the LCD device from the side of the substrate 100 toward the data line 111 travels the space between the layer 103 and the data line 111 through multiple reflections and finally, it reaches the LDD region 107b. Similarly, light is irradiated to the LDD region 107d after multiple reflections. Practically, various light including the light L103 and L104 enters from the side of the substrate 100 and thus, the light is irradiated to the channel region 107c. 
To avoid this problem, various improvements have ever been developed and disclosed.
For example, the Japanese Non-Examined Patent Publication No. 2000-180899 published in June 2000 discloses a LCD device, in which the ends of the lower light-shielding layer are tapered to form a trapezoidal cross section. In this device, if the width of the lower light-shielding layer and the width of the data line are well adjusted, light entering the LCD device from the side of the TFT array substrate is blocked by the lower light-shielding layer and thus, the light is prevented from being irradiated to the channel region.
The Japanese Non-Examined Patent Publication No. 2000-356787 published in December 2000 discloses a LCD device, in which dummy contact holes are formed near the channel region in the dielectric layer that covers the lower light-shielding layer. The dummy contact holes are filled with a wiring material. In this device, the wiring material filled in the dummy contact holes block the light entering the LCD device from the side of the TFT array substrate and thus, the light is prevented from being irradiated to the channel region.
Additionally, as known well, the black matrix layer may be placed on the TFT array substrate or the opposite substrate. If the black matrix layer is placed on the opposite substrate, an alignment error (i.e., allowance) of approximately 10 μm needs to be considered in advance in the coupling process of the TFT array substrate and the opposite substrate, while taking the typical overlay accuracy between these two substrates into consideration. As a result, the black matrix layer needs to be larger in width. This leads to a disadvantage that the aperture ratio is unable to be increased.
Unlike this, if the black matrix layer is placed on the TFT array substrate, the alignment accuracy between the black matrix layer and the TFTs can be raised by utilizing the known fabrication processes of semiconductor devices. Therefore, as shown in FIGS. 1, 2A, and 2B, this structure is becoming a main stream.
As explained above, with the prior-art LCD device having the prior-art TFT array substrate 100 of FIGS. 1 and 2A to 2B, part of the light entering the LCD device from the side of the substrate 100 is likely to reach the LDD regions 107b and 107d and/or the channel region 107c. Thus, optically induced current leakage increases and as a result, a problem of degradation of contrast and non-uniformity of image quality occurs.
With the LCD device disclosed by the Publication No. 2000-180899, the process step of forming the tapered ends of the lower light-shielding layer is required. Therefore, there is a problem that the fabrication processes are complicated.
With the LCD device disclosed by the Publication No. 2000-356787, the process step of forming the dummy contact holes near the channel region in the dielectric layer that covers the lower light-shielding layer and the process step of filing the dummy contact holes with the wiring material. Therefore, there is a problem that the fabrication processes are complicated, which is the same as that of the Publication No. 2000-180899.
Furthermore, with the LCD devices disclosed by the Publication Nos. 2000-180899 and 2000-356787, if these devices are applied to the light bulb for high-luminance projection-type display devices, it is difficult to effectively and sufficiently block the light traveling toward the active layer of the TFT.